The low resistivity and the ease of formation have made cobalt disilicide a suitable choice as the contact material to the source, drain and gate of a transistor in ultra-large scale integration (ULSI). The main drawbacks of using cobalt disilicide over the more widely used titanium disilicide reside in an increase in junction leakage and a higher sensitivity to oxygen. It is an accepted principle that the increased junction leakage is caused by the roughness of the interface between the disilicide and the Si-containing substrate.
In the self-aligned silicide (salicide) process, a blanket TiN/Co film is deposited over the devices and annealed to form cobalt monosilicide over the exposed Si regions (source, drain and gate) of the transistor. A selective wet etch process is used to remove the TiN cap and any non-reacted cobalt left over in the oxide or nitride regions. The cobalt monosilicide is then further annealed to form cobalt disilicide.
The leakage observed during electrical testing is at least partially a consequence of disilicide spikes that extend into the silicon and through the junction. Since the silicide is formed by a reactive diffusion mechanism, roughening is expected at the formation of each of the silicide phases. Presently, it is not known which of the annealing stages contribute to the formation of the most damaging interface roughness. The first phase forms a metal rich Co2Si phase during which cobalt is the main diffusing element. This phase is followed closely in temperature by formation of the monosilicide (CoSi) during which silicon is the dominant diffusing species, At higher temperature, cobalt diffusion is mainly responsible for the formation of the disilicide (CoSi2).